The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for dynamic row-width memory.
Dynamic random access memory (DRAM) devices may employ wide row width arrays and sense logic. For example, a typical 1 GB DRAM device may have eight banks, each with 8192 columns and 16,384 rows. There are significant energy inefficiencies associated with this memory organization for typical usage scenarios, because typically only a fraction of the bits transferred from the DRAM array to the sense logic are sent out of the device before the row is written back to the array. The memory must power the sense amps for the entire row, even though the server may only read data from a small number of columns. Also, the memory must pre-c (write back) the entire row on a new row select.
Reads from DRAM cells are destructive (the charge in the cell that represents a 0 or 1 is drained from the cell into the sense amps as part of the read operation). Thus, the values in the sense amps must be written back before that row can be “closed.” This write back is referred to as a “pre-charge” operation.
In open page mode, the memory may wait for a next access to determine whether to pre-charge (write back) the data stored in the sense amps to its associated portion of the DRAM array (cells). If the next access is to the same row, then the data will already be in the sense amps and can be returned immediately. If the next access is to a different row, then there is added latency as the memory stores the data in the sense amps back to the storage array, and then loads the data for the newly requested row into the sense amps before returning the requested data.
In burst mode, the memory transfers a length of bits from the same row. However, even in burst mode, the memory typically transfers far fewer than 8192 bits.